Agents that take your block from spec to silicon-ready.
DesignAgents writes the RTL, builds the UVM environment, runs real Verilator simulations and debugs the failures — inside one IDE, on one project tree, with every result traced back to a requirement.
- 4
- specialised agents
- 1
- shared project state
- 0
- fabricated results
- specextracted 16 requirements → /docs/architecture.md
- rtlwrote /rtl/mux4to1.sv (REQ-001 … REQ-009)
- dvwrote /tb/tb_mux4to1.sv, monitor, scoreboard
- simverilator --trace → UVM_ERROR @ 64000ps
- debugfixed select decode, re-ran → PASS · 0 errors
Each agent hands off to the next on the same files.
Spec Agent
Turns a plain-English block description into a numbered requirement set, micro-architecture notes and a file plan.
Design Agent
Writes synthesizable SystemVerilog against each requirement, then compiles it before handing off.
Verification Agent
Builds the UVM environment — interface, driver, monitor, scoreboard, sequences, coverage — on the same project state.
Debug Agent
Reads the failing UVM log, points the waveform cursor at the failure time, applies a minimal fix and re-runs.
Everything the agents need is already in the IDE.
A real multi-file project
Collapsible /rtl, /tb and /docs tree, Monaco editing, create, rename and delete — agents work on the same files you do.
Agents run Verilator themselves
The agent compiles and simulates, then reads the log it gets back. Pass or fail comes from a simulator, not from prose.
Real VCD waveforms
Runs dump traces automatically. Browse single-bit and bus signals, zoom, and drop the cursor on the failing timestamp.
Requirement traceability
Every REQ maps to the RTL that implements it and the test that proves it, with the last run status attached.
Synthesis handoff bundle
Export a zip with /rtl, /verif, /docs, SDC constraints, lint report, coverage summary and a requirements matrix.
Persistent project hub
Every file, spec and run is saved per project, with pipeline stage, last result and file counts on one page.
From a paragraph to a verification plan
Describe your block. The Spec Agent extracts every requirement into a traceability table and flags what you didn't say but need — edge cases, timing budgets, reset behaviour.
Synthesizable RTL, compiled before it ships
The Design Agent implements each requirement in SystemVerilog, writes it straight into the project tree, then compiles and runs it — no RTL is handed over untested.
Export a synthesis handoff bundle in one click
Every project exports as a structured zip your synthesis and sign-off flow can consume directly — constraints, lint, coverage and traceability included.
- ├─/rtl/mux4to1.sv
- ├─/verif/tb_mux4to1.sv
- ├─/constraints/mux4to1.sdc
- ├─/reports/lint_report.txt
- ├─/reports/coverage_summary.html
- ├─/docs/requirements_matrix.csv
- ├─/README.md
Every result is a real simulation
Real Verilator compiles and runs
Not narrated output. If it says PASS, a simulator actually ran and passed.
Full requirement traceability
Every line of RTL and every test maps back to a numbered requirement in your spec.
The agent never fabricates results
It's explicitly instructed to report only what the simulator actually returns.